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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by J112/D JFET Chopper Transistor N-Channel -- Depletion 1 DRAIN 3 GATE J112 2 SOURCE MAXIMUM RATINGS Rating Drain - Gate Voltage Gate - Source Voltage Gate Current Total Device Dissipation @ TA = 25C Derate above 25C Lead Temperature Operating and Storage Junction Temperature Range Symbol VDG VGS IG PD TL TJ, Tstg Value - 35 - 35 50 350 2.8 300 - 65 to +150 Unit Vdc Vdc mAdc mW mW/C C C CASE 29-04, STYLE 5 TO-92 (TO-226AA) 1 2 3 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Max Unit OFF CHARACTERISTICS Gate - Source Breakdown Voltage (IG = -1.0 Adc) Gate Reverse Current (VGS = -15 Vdc) Gate Source Cutoff Voltage (VDS = 5.0 Vdc, ID = 1.0 Adc) Drain-Cutoff Current (VDS = 5.0 Vdc, VGS = -10 Vdc) V(BR)GSS IGSS VGS(off) ID(off) 35 -- - 1.0 -- -- - 1.0 - 5.0 1.0 Vdc nAdc Vdc nAdc ON CHARACTERISTICS Zero-Gate-Voltage Drain Current(1) (VDS = 15 Vdc) Static Drain-Source On Resistance (VDS = 0.1 Vdc) Drain Gate and Source Gate On-Capacitance (VDS = VGS = 0, f = 1.0 MHz) Drain Gate Off-Capacitance (VGS = -10 Vdc, f = 1.0 MHz) Source Gate Off-Capacitance (VGS = -10 Vdc, f = 1.0 MHz) 1. Pulse Width = 300 s, Duty Cycle = 3.0%. IDSS rDS(on) Cdg(on) + Csg(on) Cdg(off) Csg(off) 5.0 -- -- -- 50 28 mAdc pF -- -- 5.0 5.0 pF pF (Replaces J111/D) Motorola Small-Signal Transistors, FETs and Diodes Device Data (c) Motorola, Inc. 1997 1 J112 TYPICAL SWITCHING CHARACTERISTICS 1000 t d(on), TURN-ON DELAY TIME (ns) 500 200 100 50 20 10 5.0 RK = 0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 50 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 50 RK = RD TJ = 25C VGS(off) = 7.0 V t r , RISE TIME (ns) 1000 500 200 100 50 20 10 5.0 RK = 0 RK = RD TJ = 25C VGS(off) = 7.0 V Figure 1. Turn-On Delay Time Figure 2. Rise Time 1000 t d(off) , TURN-OFF DELAY TIME (ns) 500 200 100 50 20 10 5.0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) RK = 0 RK = RD TJ = 25C VGS(off) = 7.0 V t f , FALL TIME (ns) 1000 500 200 100 50 20 10 5.0 2.0 RK = 0 RK = RD TJ = 25C VGS(off) = 7.0 V 20 30 50 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 50 Figure 3. Turn-Off Delay Time Figure 4. Fall Time NOTE 1 +VDD RD SET VDS(off) = 10 V INPUT RGEN 50 50 VGEN RK RT OUTPUT RGG VGG 50 INPUT PULSE tr 0.25 ns tf 0.5 ns PULSE WIDTH = 2.0 s DUTY CYCLE 2.0% RGG & RK RD (R ) 50) + RRD) TRT ) 50 D Figure 5. Switching Time Test Circuit The switching characteristics shown above were measured using a test circuit similar to Figure 5. At the beginning of the switching interval, the gate voltage is at Gate Supply Voltage (-VGG). The Drain-Source Voltage (VDS) is slightly lower than Drain Supply Voltage (VDD) due to the voltage divider. Thus Reverse Transfer Capacitance (Crss) or Gate-Drain Capacitance (Cgd) is charged to VGG + VDS. During the turn-on interval, Gate-Source Capacitance (C gs) discharges through the series combination of RGen and RK. Cgd must discharge to VDS(on) through RG and RK in series with the parallel combination of effective load impedance (R D ) and Drain-Source Resistance (rds). During the turn-off, this charge flow is reversed. Predicting turn-on time is somewhat difficult as the channel resistance rds is a function of the gate-source voltage. While Cgs discharges, VGS approaches zero and rds decreases. Since Cgd discharges through rds, turn-on time is non-linear. During turn-off, the situation is reversed with rds increasing as Cgd charges. The above switching curves show two impedance conditions; 1) RK is equal to RD, which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) RK = 0 (low impedance) the driving source impedance is that of the generator. 2 Motorola Small-Signal Transistors, FETs and Diodes Device Data y fs, FORWARD TRANSFER ADMITTANCE (mmhos) J112 20 15 10 10 7.0 5.0 Tchannel = 25C VDS = 15 V C, CAPACITANCE (pF) Cgs 7.0 5.0 Cgd 3.0 2.0 0.5 0.7 3.0 2.0 1.5 Tchannel = 25C (Cds IS NEGLIGIBLE) 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 50 1.0 0.03 0.05 0.1 0.3 0.5 1.0 3.0 5.0 VR, REVERSE VOLTAGE (VOLTS) 10 30 Figure 6. Typical Forward Transfer Admittance Figure 7. Typical Capacitance 200 rds(on), DRAIN-SOURCE ON-STATE RESISTANCE (OHMS) rds(on), DRAIN-SOURCE ON-STATE RESISTANCE (NORMALIZED) IDSS = 10 160 mA 25 mA 50 mA 75 mA 100 mA 125 mA 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 - 70 - 40 - 10 20 50 80 110 Tchannel, CHANNEL TEMPERATURE (C) 140 170 ID = 1.0 mA VGS = 0 120 80 Tchannel = 25C 40 0 0 1.0 2.0 3.0 4.0 5.0 6.0 VGS, GATE-SOURCE VOLTAGE (VOLTS) 7.0 8.0 Figure 8. Effect of Gate-Source Voltage On Drain-Source Resistance Figure 9. Effect of Temperature On Drain-Source On-State Resistance 100 rds(on), DRAIN-SOURCE ON-STATE RESISTANCE (OHMS) 90 80 70 60 50 40 30 20 10 9.0 8.0 VGS, GATE-SOURCE VOLTAGE (VOLTS) Tchannel = 25C 10 NOTE 2 The Zero-Gate-Voltage Drain Current (IDSS), is the principle determinant of other J-FET characteristics. Figure 10 shows the relationship of Gate-Source Off Voltage (VGS(off) and Drain-Source On Resistance (rds(on)) to IDSS. Most of the devices will be within 10% of the values shown in Figure 10. This data will be useful in predicting the characteristic variations for a given part number. For example: Unknown rds(on) and VGS range for an J112 The electrical characteristics table indicates that an J112 has an IDSS range of 25 to 75 mA. Figure 10, shows rds(on) = 52 Ohms for IDSS = 25 mA and 30 Ohms for IDSS = 75 mA. The corresponding VGS values are 2.2 volts and 4.8 volts. rDS(on) @ VGS = 0 VGS(off) 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 IDSS, ZERO-GATE-VOLTAGE DRAIN CURRENT (mA) Figure 10. Effect of IDSS On Drain-Source Resistance and Gate-Source Voltage Motorola Small-Signal Transistors, FETs and Diodes Device Data 3 J112 PACKAGE DIMENSIONS A R P SEATING PLANE B F L K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. DIMENSION F APPLIES BETWEEN P AND L. DIMENSION D AND J APPLY BETWEEN L AND K MINIMUM. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. INCHES MIN MAX 0.175 0.205 0.170 0.210 0.125 0.165 0.016 0.022 0.016 0.019 0.045 0.055 0.095 0.105 0.015 0.020 0.500 --- 0.250 --- 0.080 0.105 --- 0.100 0.115 --- 0.135 --- MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.41 0.55 0.41 0.48 1.15 1.39 2.42 2.66 0.39 0.50 12.70 --- 6.35 --- 2.04 2.66 --- 2.54 2.93 --- 3.43 --- XX G H V 1 D J C SECTION X-X N N DIM A B C D F G H J K L N P R V CASE 029-04 (TO-226AA) ISSUE AD STYLE 5: PIN 1. DRAIN 2. SOURCE 3. GATE Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 INTERNET: http://motorola.com/sps 4 J112/D Motorola Small-Signal Transistors, FETs and Diodes Device Data |
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